The present invention relates to a semiconductor device and its manufacturing method. More particularly, the present invention relates to a technique effectively applied to a semiconductor device in which substrates each mounting a semiconductor chip are stacked.
In the manufacture of a semiconductor device, semiconductor elements or line patterns are collectively formed in a plurality of element forming regions provided in a wafer made of single crystal silicon etc. so as to form a predetermined circuit; and the wafer is trimmed along a scribing region between the adjacent element forming regions and there is performed dicing by which the respective element forming regions are separated as individual semiconductor chips. Thereafter, through an assembly process such as a bonding process for fixing the separated individual semiconductor chips to a base substrate and an encapsulation process such as resin encapsulation, the manufacture of a semiconductor device is completed.
For example, in a semiconductor memory device such as a DRAM, larger memory capacity or a space-saving semiconductor memory device with predetermined memory capacity has been demanded. In order to meet such a demand, there has been invented an SIP (System In Package) in which a plurality of semiconductor chips are encapsulated in a single encapsulation body. In this SIP, since a plurality of semiconductor chips to be used must be all good (non-defective) chips KGD (Known Good Dic) and a technique for sorting good products in bare chips has not been sufficiently established, there has been invented such a method that sorting testing of the semiconductor chip is carried out in a state of being attached to a substrate and only the substrates to each of which a good semiconductor hip in attached are stacked.
The substrate as mentioned above is composed of an insulating substrate made of polyimide etc. on which leads each made of a metal film are formed, and one ends of the leads are connected to pads of the semiconductor chip and the other ends of the leads are connected to connection terminals of the substrate. The bump electrodes formed on the connection terminals are used to connect each of the substrates. The semiconductor chip in fixed to the substrate by an adhesive layer, and the connecting portions between the leads and the pads are covered with an encapsulation material such as a resin.
In the case of connecting each of the semiconductor chips thus stacked and assembled, the terminals common to the respective semiconductor chips such as address lines among the terminals of the semiconductor chips can be connected in parallel by using the same line patterns. However, an individual line must be prepared for the terminal specific to each semiconductor chip, and the substrates each having different line patterns must be prepared for each layer.
Therefore, Japanese Patent Laid-Open No. 2-198148 (Japanese Patent No. 2695893) discloses a technique for providing a plurality of leads connected to the semiconductor chip and selecting a proper lead from the leads.